The inventions relate to a semiconductor memory cell, array, architecture and device, and techniques for controlling and/or operating such cell, array and device; and more particularly, in one aspect, to a dynamic random access memory (“DRAM”) cell, array, architecture and device, wherein the memory cell includes an electrically floating body wherein an electrical charge is stored therein.
There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Semiconductor-on-Insulator (SOI) is a material in which such devices may be fabricated or disposed on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET.
One type of dynamic random access memory cell is based on, among other things, the electrically floating body effect of SOI transistors. (See, for example, U.S. Pat. No. 6,969,662). In this regard, the dynamic random access memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation layer (or non-conductive region, for example, in a bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor.
With reference to FIGS. 1A, 1B and 1C, in one embodiment, semiconductor DRAM array 10 includes a plurality of memory cells 12 each consisting of transistor 14 having gate 16, body region 18, which is electrically floating, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in an SOI material/substrate) or non-conductive region (for example, in a bulk-type material/substrate). The insulation or non-conductive region 24 may be disposed on substrate 26.
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. Notably, the entire contents of the '662 patent, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein.
The memory cell 12 of DRAM array 10 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 34 from body region 18. (See, for example, the N-channel transistor in FIGS. 2A and 2B). In this regard, conventional write techniques may accumulate majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 by, for example, impact ionization near source region 20 and/or drain region 22. (See, FIG. 2A). The majority carriers 30 may be emitted or ejected from body region 18 by, for example, forward biasing the source/body junction and/or the drain/body junction. (See, FIG. 2B).
Notably, for at least the purposes of this discussion, logic high or logic “1” corresponds to, for example, an increased concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic low or logic “0”. In contrast, logic low or logic “0” corresponds to, for example, a reduced concentration of majority carries in the body region relative to an unprogrammed device and/or a device that is programmed with logic high or logic “1”.
Conventional reading is often performed by applying a small drain bias and a gate bias above the transistor threshold voltage. A sense amplifier senses, detects and/or samples the drain current which is determined or influenced by the charge stored in the electrically floating body of the transistor of the memory cell thereby giving a possibility to distinguish between the data states (for example, state “1” and state “0”). A floating body memory device may have two different current “states” corresponding to the two different logical states “1” and “0”.
Notably, when the difference in electrical characteristic between two states is small and/or variable, a tracking reference may be employed for correct recovery of the stored digital data during a read operation. In this regard, a midpoint reference is often used so as to position the reference halfway between the characteristics of two adjacent digital states. This midpoint reference is classically constructed using two memory cells storing the two adjacent digital states. For instance, in a dynamic random access memory (DRAM) making use of Silicon-On-Insulator (SOI) floating body memory cells, a cell storing state “0” and a cell storing state “1” are placed in parallel and biased appropriately such as to provide a sum of the two corresponding currents. This term is then divided by two to generate a midpoint reference level used to discriminate the state of a read memory cell inside the array. (See, FIG. 3).
However, unavoidable variations typically exist in commercial devices because of mismatch in memory cell characteristics as well as mismatch in the transistors that comprise the circuitry (for example, the sense amplifier circuitry) which is responsible for sensing, sampling, detecting and/or discriminating between the data states. This tends to reduce the margin of operation (for example, the read window margin). To minimize this issue, a common practice is the use of a plurality of reference cells in parallel, thus decreasing the overall variance of the reference characteristic. (See, FIG. 3).
Notably, the concerns regarding mismatch are often exacerbated when implementing deep sub-micron technologies. It has been reported that the variance of an electrical characteristic increases with the absolute value of the electrical characteristic (although diminishing in relative terms). (See for example: “Understanding MOSFET Mismatch for Analog Design” by Drennan et al., IEEE J. Solid-State Circuits, vol. 38, pp. 450-456, March 2003). As a result, the variance of the various electrical characteristics corresponding to the different digital states may not be constant. With that in mind, in relation to the SOI floating body DRAM example, these current corresponding to a read operation of the memory cells storing state “1”, the reference, and state “0” affected by their respective variance and measured at the sense amplifier level are depicted in FIG. 4. Prior art midpoint reference positioning may also exhibit the drawback of having unequal read margins toward state “0” and state “1”, this latter case demonstrates a lower margin. This lower margin may eventually translate into more failures during the read operations (and/or an overall reduction in the read window margin).